The present invention relates to a semiconductor circuit, and more particularly to a BiCMOS logic circuit.
The conventionally proposed BiCMOS logic circuit outputs inverted signals of logical product and logical sum of the input signals in a NOR gate and a NAND gate, respectively, and when a logical output of OR or AND is needed, an inverted logical signal is outputted from a CMOS logic circuit 401 as shown in FIG. 1, and inputted into a BiCMOS inverter circuit of 402 to obtain a normal signal as an output from the BiCMOS circuit.
In FIG. 1, the inputs A, B and C are outputted from the CMOS logic circuit 401 as A.multidot.B+C, and by inverting the same once again at the BiCMOS logic inverter 402, an output of A.multidot.B+C and be obtained.
At the time of designing an integrated circuit, an error in estimating the load wiring length may result in insufficient driving capacity of the logic circuit and a buffer circuit capable of high capacitance driving at a high speed may have to be inserted between an output of the logic circuit and the load wiring. Since there are no circuits where inputs and outputs are in the same phase in a BiCMOS circuit, a CMOS inverter and an BiCMOS inverter have to be serially connected and used as a buffer circuit.
According to the method of realizing the AND (or OR) logic with the conventional circuit as mentioned above, a two-stage construction is necessary in order to further invert the logic of the NAND (or OR), resulting in an increased number of stages of the logic gates and making it difficult to increase the switching speed. Similar difficulty in increasing the speed is also found when a buffer circuit of the same phase is constructed with a CMOS inverter+BiCMOS inverter because of increased number of logical gate stages.